CCD Array with Integrated High Voltage Protection Circuit

ABSTRACT

A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a plurality of gate electrodes that are insulated from the substrate by an insulating layer. The gate electrodes are connected to a conductor bonded to the substrate. The protection circuit is also constructed on the substrate. The protection circuit is connected to the conductor and to the substrate and protects the CCD array from both negative and positive voltage swings generated by electrostatic discharge events and the like. The protection circuit and the CCD can be constructed in the same integrated circuit fabrication process.

BACKGROUND OF THE INVENTION

Integrated circuits are subject to damage from electrostatic discharge(ESD) events. A person can cause such an event by touching an input leadto a device or a conductor connected to that lead. Such discharges arecharacterized by voltages in the kilovolt range and instantaneouscurrents in the ampere range. As circuit geometries are reduced toprovide faster and more complex integrated circuits, the vulnerabilityof the integrated circuits to such events increases.

To protect such circuits, a protection circuit is often attached to theinput pads on the chip. The circuit shorts the pad to the substrate onthe chip if the voltage on the pad exceeds a predetermined value.Numerous protection circuits for use in CMOS circuitry are known to theart. The simplest form of ESD protection circuit consists of one or morediodes connected in series to form a chain that is connected between thepad and the substrate. As long as the voltage on the pad is less thanthe diode threshold, little current flows from the pad to ground throughthe diode chain. If the voltage is greater than the diode threshold ofthe chain, the circuit will conduct charge from the pad to ground, andhence, prevent the voltage on the pad from increasing much beyond thediode threshold. The voltage at which the chain conducts is determinedby the number of diodes in the chain.

Unfortunately, these circuits cannot be used in charge-coupled devices(CCDs). Imaging chips that are utilized in a wide range of cameradevices are based on CCD arrays. The CCD structure can be viewed as anumber of columns that are divided into pixels whose boundaries can bemoved to read out the charge by shifting the charge down the columns.The boundaries of the pixels and the charge shifting mechanism areimplemented with a plurality of gates that overlie the portion of thesubstrate in which the columns are located. Each pixel on the chip has aplurality of gates. The gates are separated from the substrate by a thinoxide layer. If the potential difference between the gates and thesubstrate is sufficiently high, the oxide layer can be damaged. Forexample, a short can be formed from the gate to the substrate. As willbe discussed in more detail below, each gate belongs to a specificclass, and all of the gates in a class are connected together. Hence,such a short effectively shorts all of the gates in that class andrenders the chip, or a large portion thereof, inoperative. Even if theresultant oxide damage does not short the gate to the substrate, theoxide damage can result in long-term reliability problems that lead topremature device failure. Unlike CMOS circuitry, CCD designs do not lendthemselves to the inclusion of spare rows and/or columns that can beconnected after fabrication to correct problems such as the gate tosubstrate shorts discussed above.

The gates in a CCD must be switched to both positive and negativepotentials with respect to the substrate. Hence, a pad on the CCD usedto drive the gates must be able to swing between −V1 and +V2 without asignificant current flowing between the pad and substrate. However, ifthe voltage is significantly less than −V1 or greater than V2, the ESDprotection circuit must be actuated to short the excess current to thesubstrate.

If a diode structure such as that described above is utilized to protectthe circuit from voltage excursions above V2, the protection circuitwill begin to conduct when the voltage on the pad goes above V2 orswings to a potential below 0. Hence, the protection circuit would shortcircuit the pad during the operation of the device when the pad isrequired to swing to −V1. In principle, this problem could be solved byutilizing a protection circuit consisting of two zener diodes ofopposite polarity connected in series. However, construction of suchpairs of diodes in the fabrication process used to construct CCD arraysis not practical.

It should also be noted that the CCD array can be damaged by chargebuildup at a number of points in its fabrication or incorporation into alarger device in addition to the ESD events discussed above. Typically,the CCD chip is fabricated and then bonded to another substrate thatincludes the drive circuitry for the various electrodes. Damage fromevents that occur after the bonding to the drive substrate can bereduced by incorporating protection devices on the drive substrate. Suchcircuitry is not subject to the same fabrication limitations that limitthe fabrication of the protection circuit on the CCD chip itself, andhence, conventional protection circuits can be utilized. However,protection circuitry on the drive substrate does not prevent damage thatoccurs prior to the bonding process. The CCD is subject to ESD duringthe handling of the wafers prior to bonding and during the bondingprocesses. In addition, some of the etching processes utilized after theelectrodes have been fabricated over the oxide layer can lead to acharge buildup on the electrodes. This charge buildup can also damagethe oxide layer.

SUMMARY OF THE INVENTION

The present invention includes a CCD circuit and method for making thesame. The circuit includes a CCD array and a protection circuit. The CCDarray is constructed on an integrated circuit substrate and includes aplurality of gate electrodes that are insulated from the substrate by aninsulating layer. The gate electrodes are connected to a conductorbonded to the substrate. The protection circuit is also constructed onthe substrate. The protection circuit is connected to the conductor andto the substrate. The protection circuit has a first state in which theprotection circuit provides an impedance greater than an operatingimpedance between the conductor and the substrate and a second state inwhich the protection circuit provides a shorting impedance between theconductor and the substrate. The protection circuit is in the firststate if the potential on the conductor is in an operating range definedby a negative threshold potential and a positive threshold potential,and the protection circuit is in the second state if the potential onthe conductor is outside the operating range. The protection circuit andthe CCD can be constructed in the same integrated circuit fabricationprocess.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a CCD imaging sensor chip according to one embodimentof the present invention.

FIG. 2 illustrates the output end of shift register 20 and outputamplifier 30 in a four-phase CCD.

FIGS. 3A-3E illustrate one type of protection circuit according to thepresent invention.

FIGS. 4A-4C are schematic drawings of three embodiments of a protectioncircuit according to the present invention for use with an NMOS CCDarray.

FIGS. 5A-5C are schematic drawings of three protection circuitsaccording to the present invention that could be used with a PMOS CCDarray.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

The present invention utilizes protection circuits that are fabricatedon the CCD chip using the limited fabrication processes that areavailable in the CCD fabrication process. The protection circuits areoperative to protect the oxide layer from charge buildup or ESD eventsthat occur after the drive lines are connected to the protectiondevices, and hence, the CCD device is protected from some of the chargebuildup that occurs in the etching processes in the later stages of thedevice fabrication as well as ESD events that occur after the protectioncircuit is connected to the gates.

The manner in which the present invention provides its advantages can bemore easily understood with reference to FIG. 1, which illustrates a CCDimaging sensor chip according to one embodiment of the presentinvention. Image sensor 10 includes a photodetector array 11 in whichthe individual photodetectors 15 are organized as a plurality of rows 12and columns 13. The boundaries of each photodetector are defined by anumber of gates that are fabricated over the column in which thephotodetector is located. In addition, the columns can be operated asshift registers to move charge stored in the various photodetectorsafter the array is exposed to an image, to shift register 20 bymanipulating the potentials on the gates in that column. On each columnshift operation, the contents of the photodetectors in row 21 areshifted into register 20, and the contents of each column are moveddownward toward shift register 20. The contents of shift register 20 arethen shifted horizontally into an output amplifier 30 that converts thecharge in cell 25 to an output voltage in an analogous manner.

Each pixel has a plurality of gates that are used to define the pixelarea within the column in which the pixel resides. The boundaries of thecolumns along the long sides of the columns are defined by implants.These gates consist of electrodes that are also used to shift the chargein a pixel along the columns during a readout operation. The number ofelectrodes varies according to the specific chip design. However, thecorresponding electrodes in each pixel are connected together and aredriven by off-chip circuits that are connected to drive lines via aninterface 18 comprising a plurality of signal pads 17. Each signal padis connected to the chip substrate by a protection circuit 16. Tosimplify the drawing, the various electrodes used in the shiftingoperations have been omitted from FIG. 1.

Refer now to FIG. 2, which illustrates the output end of shift register20 and output amplifier 30 in a typical four-phase CCD. The shiftingoperation along the columns that deposits charge into shift register 20operates in a manner analogous to that described below for shiftregister 20. The manner in which charge is shifted along shift register20 is known to the art, and hence, will not be discussed in detail here.For the purposes of this discussion, it is sufficient to note that eachcell in shift register 20 includes an area of silicon in which thecharge moves, and 4 electrodes that set the profile of potentials inthat silicon area. Two such cells are shown at 25 and 26. The electrodesover the silicon area 37 of cell 26 are shown at 41-44. At the start ofa shift cycle, the electrodes 41 and 44 are at potentials that containthe charge in the region under electrodes 42 and 43. To move the chargeinto amplifier 30, the potential at electrode 42 is altered to force thecharge into the region under electrode 44. The potential on electrodes44 and 49 is then altered to allow the charge to escape onto capacitor31 at the input to amplifier 32. The potential on electrodes 43 and 44is then sequentially altered to force the charge under these electrodesto move onto capacitor 31. It should be noted that the potential onelectrode 49, which acts as an output gate, is maintained at a constantpotential. This output gate reduces clock coupling between the otherelectrodes and capacitor 31.

During the shift operation, the potentials on electrodes 45-48associated with cell 25 are likewise manipulated to force the charge incell 25 into cell 26. For example, when the potential on electrode 42 isaltered to force charge under that electrode to the area under electrode43, electrode 41 is no longer needed to contain the charge within cell26. Hence, the potential on this electrode can be altered to allowcharge from cell 25 to move under electrode 41. Similarly, when thepotential on electrode 43 is altered to move the charge under electrode44, the potential on electrode 42 is no longer needed to separate thecharge in cells 25 and 26, and hence this electrode's potential can bealtered to allow the charge from cell 25 to move under that electrode.The potential on the electrodes in cell 25 can then be altered to forcethe remaining charge from cell 25 to move under electrode 43 therebycompleting the shifting of the charge from cell 25 to cell 26 while thecharge from cell 26 was shifted onto capacitor 31.

As noted above, during the shifting operations, the potential on thevarious electrodes varies between a −V1 and +V2. In a multiphase pinnedoperation the typical high voltage on the vertical CCD gates is 5 voltsand the typical low voltage is −8 volts. Hence, the protection circuitsshown in FIG. 1 must not present a source of significant leakage currentfor either polarity within this range. However, the protection circuitsshown at 16 in FIG. 1 must operate to short a signal less than −V3 orgreater than V4 to ground, where −V3<−V1 and V4>V2.

In addition, the protection circuits must be of a type that can befabricated in the same fabrication system as that used to construct thevarious shift registers, electrodes, and other circuitry on chip 10.CCDs require high charge-transfer efficiency. To achieve thisefficiency, CCDs are fabricated using specialized processes thatminimize imperfections in the semiconductor material. Most logiccircuitry relies on CMOS fabrication techniques. In general, thefabrication processes used to produce CCD and CMOS imagers areincompatible. For example, conventional CMOS fabrication processesrequire complex shallow implants and isolation that lead to unacceptableimperfections in the underlying semiconductor materials. While generallyacceptable in CMOS devices, these imperfections typically reduce theefficiency of CCD devices to unacceptable levels.

CCD devices are typically manufactured in an NMOS or PMOS process. Ifthe CCD is an NMOS device, NMOS FET transistors, N type JFETs, PNPbipolar transistors, and NPN bipolar transistors with their basesshorted to ground can be fabricated; however, NPN transistors withfloating bases, P type JFETs, and PMOS FETs cannot be fabricated. Hence,the protection circuits must be constructed from PNP transistors, NPNtransistors with their bases shorted to ground, N type JFETs, and NMOStransistors, or diodes of one polarity.

Similarly, if the CCD is a PMOS device, PMOS FET transistors, P typeJFETs, and PNP transistors with their bases shorted to ground, and NPNbipolar transistors can be fabricated; however PNP bipolar transistorswith floating bases, N type JFETs, and NMOS FETs cannot be fabricated.In this case, the protection circuits must be constructed from NPNtransistors, PNP bipolar transistors with their bases shorted to ground,and PMOS transistors, or diodes of the opposite polarity.

To simplify the following discussion it will be assumed that the CCD isfabricated in NMOS. Refer now to FIGS. 3A-3E, which illustrate one typeof protection circuit according to the present invention. To simplifythe discussion, the protection circuit will be described in terms ofswitches. The first type of switch will close if the voltage differenceacross the switch is greater than a predetermined voltage Vp, which isgreater than 0. Switch 53 is of this type. The second class of switcheswill close if either of two conditions is satisfied. Referring to switch51, switch 51 closes if the potential on terminal 54 is greater than thepotential on terminal 55. In addition, switch 51 will close if thepotential on terminal 54 is less than the potential on terminal 55 by anamount that is greater than Vm, which is greater than 0. Switch 52 isalso of this type.

Protection circuit 50 utilizes 3 switches, 51-53. Switch 51 is connectedto the pad that is to be protected by terminal 54. Switches 52 and 53are connected in parallel between ground and terminal 55. It will beassumed that the substrate is held at ground. Denote the voltage on thepad relative to ground by V.

Consider the case in which the potential on the pad is positive.Referring to FIG. 3B, if V is between 0 and Vp, switch 51 will beclosed; however both switches 52 and 53 will be open, and hence, nocurrent flows from the pad to ground through the protection circuit. If,however, the potential increases above Vp, switch 53 will close as shownin FIG. 3C. Hence, the pad is protected from positive voltage spikesthat are greater than Vp.

Next, consider the case in which the potential on the pad is negative.Referring to FIG. 3D, if the potential is between ground and −Vm,switches 51 and 53 will remain open; while switch 52 will close. Hence,no current flows from the pad to ground through the protection circuit.If, however, the pad potential becomes more negative than −Vm, switch 51will close, and the pad will be shorted to ground. Hence, the pad isalso protected from negative voltage spikes having a magnitude greaterthan Vm.

As noted above, the switches in question must be fabricated in the samefabrication system as the CCD array. Refer now to FIGS. 4A-4C, which areschematic drawings of three embodiments of a protection circuitaccording to the present invention for use with NMOS CCD arrays. In allof these circuits, switches 51 and 52 are implemented with a PNP bipolartransistor. Switch 51 is the base-emitter junction of transistor 61, andswitch 52 is the collector-base junction of transistor 61. In this case,Vm is the punch through voltage between the collector and the emitter oftransistor 61.

Referring to FIG. 4A, switch 53 is also implemented with an NPN bipolartransistor with its base shorted to ground in protection circuit 60. Vpis the collector emitter punch through voltage. When the pad is between0 and Vp, the base-emitter junction of transistor 61 is forward biased,and hence, the potential on the pad is transferred to the collector oftransistor 62 which is non-conducting since it's base is held at ground.When the pad potential exceeds Vp, transistor 62 punches through andforms a low impedance path to ground thereby shorting the pad to ground.When the pad potential is between 0 and −Vm, the base-emitter junctionof transistor 61 is reverse-biased and hence will not conduct. However,when the potential decreases to below −Vm, the collector to emitterjunction will punch through; the base collector junction will be forwardbiased, and hence, the pad will be connected to ground throughtransistor 61. The values of Vm and Vp in protection circuit 60 arecontrolled by the fabrication parameters of transistors 61 and 62,respectively.

Referring now to FIG. 4B, protection circuit 65 operates in a manneranalogous to that described above. Switch 53 is implemented as a fieldeffect transistor 63. The punch through voltage for transistor 63 can betuned by applying a potential to the gate of the transistor. Hence,protection circuit 65 provides a variable Vp.

Referring now to FIG. 4C, protection circuit 66 also operates in amanner analogous to that described above. In this embodiment, switch 53is implemented as a zener diode 64 whose zener voltage is equal to Vp.

The above-described embodiments were implemented in an NMOS CCDfabrication system. Analogous circuits can be provided for use with aPMOS CCD array. In that case, switches 51 and 53 would be implemented asan NPN transistor and a PNP transistor with its base shorted to ground.Refer now to FIGS. 5A-5C, which are schematic drawings of threeprotection circuits that could be used with a PMOS CCD. Protectioncircuits 70, 75, and 76 are analogous to protection circuits 60, 65, and66, respectively. The switches 51 and 52 shown in FIG. 3A areimplemented with a PNP bipolar transistor with its base shorted toground 71. Switch 53 is implemented with an NPN bipolar transistor 72, aFET 73, and a zener diode 74, respectively in protection circuits 70,75, and 76.

Referring to FIG. 5A, when the pad is negatively biased with a potentialhaving a magnitude less than a first threshold, the emitter-basejunction of transistor 71 is forward biased, and hence, the potential istransferred to the collector of transistor 72. However, both transistor72 and the collector-base junction of transistor 71 are non-conducting,and hence, no current flows from the pad to ground. Once the potentialon the pad becomes more negative than the first threshold value,transistor 72 punches through, and current flows from the pad to ground.Similarly, when the pad is at a positive potential below a secondthreshold value, the emitter-base junction of transistor 71 isreverse-biased, and hence, non-conducting. In this case, no currentflows from the pad to ground. However, when the potential on the padexceeds this threshold, transistor 71 punches through, and current flowsfrom the pad to ground. Protection circuits 75 and 76 operate in asimilar manner, and hence, will not be discussed in detail here.

In one embodiment of the present invention, the protection circuit isfabricated in the same process as the CCD. The CCD electrodes aretypically constructed of polysilicon. As noted above, each pixel has aplurality of electrodes. The corresponding electrodes in each pixel areconnected to a common drive line that connects the electrodes in eachcolumn to a common drive line. The drive lines run at right angles tothe columns. If there are 4 electrodes per pixel, and N pixels percolumn, there will be 4N such drive lines. The 4N drive lines areconnected to 4 electrodes at the edge of the sensor. The drive lines aretypically etched from the first metal layer in the fabrication process.The protection circuit is completed by the time the polysiliconelectrodes are completed. Hence, when the first metal layer isdeposited, the CCD electrodes are electrically connected to theprotection circuits. Initially, all of the electrodes are connected toall of the protection circuits, since the individual drive lines havenot yet been etched from the metal layer.

The CCD electrodes are floating gates, and hence, any charge that isdeposited on the electrodes during subsequent processing can result in apotential between the electrodes and the substrate that is sufficient todamage the gate oxide that separates the electrodes from the substrate.During the etching of the various metal layers to form individualconductors, electrostatic charges can build up on the electrodes. Inthis embodiment of the present invention, a large voltage that builds upon the electrodes is discharged to ground by the protection circuitthrough the metal layer. Hence, the CCD is protected from such chargebuild up once the first metal layer is deposited.

In addition, the CCD chip is protected from ESD events that occur afterthe first metal layer is deposited. Some CCD imaging arrays areconstructed from a CCD array and a second substrate that includes thecircuitry that drives the various electrodes and processes the chargethat is shifted off of the CCD array. These two substrates arefabricated separately and then bonded together by solder bump bonding orother techniques. During the handling of the CCD array chip prior to thecompletion of the bonding of the CCD chip to the second substrate, theCCD chip is vulnerable to damage from ESD events. The present inventionprovides protection from the ESD events that occur after the first metallayer has been deposited.

It should be noted that, in principle, a protection circuit of aconventional design could be incorporated in the second substrate.However, in contrast to the present invention, such a protection circuitcannot protect the CCD array from the types of damage discussed abovethat can occur prior to the bonding of the CCD chip to the secondsubstrate. Hence, the present invention provides a substantialimprovement over prior art techniques for protecting CCD arrays.

In the above-described embodiments of the present invention, theswitches have been described in terms of devices that are either open,and hence, provide infinite impedance, or closed, and hence, provide aperfect short between their terminals. However, it will be appreciatedby those skilled in the art that the protection circuit can have finiteimpedances and still function satisfactorily. A protection circuitaccording to the present invention has two states. In the first state,the protection circuit provides an operating impedance between theconductor and the substrate. The operating impedance is defined to be animpedance greater than the impedance at which the leakage currentthrough the protection circuit would interfere with the operation of thenormal CCD array.

In the second state, the protection circuit provides a shortingimpedance between the conductor and the substrate. The shortingimpedance is defined to be any impedance that is less than the impedanceat which the CCD array would be damaged if the conductor were raised toa potential outside the operating range of the CCD by a predeterminedESD event or a predetermined level of charge buildup during thefabrication process. It will be appreciated that these design parameterswill depend on the individual CCD design and the anticipated environmentin which the CCD is fabricated and designed to operate. A typical ESDevent is modeled using the “human body model”, a 100 pF capacitance with2000 volts across it in series with a 1 K ohm load, must be shorted toany pin on the CCD without causing damage. Damage to CCD gates is afunction of gate oxide thickness, but it typically occurs above +/−30volts in reference to the substrate.

Various modifications to the present invention will become apparent tothose skilled in the art from the foregoing description and accompanyingdrawings. Accordingly, the present invention is to be limited solely bythe scope of the following claims.

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 8. A method for fabricating a CCD device on asubstrate comprising: fabricating a CCD array and a protection circuiton said substrate using the same fabrication process, said CCD arraycomprising a plurality of gate electrodes that are connected to saidprotection device by a conductor, said protection circuit beingconnected to said conductor and to said substrate, said protectioncircuit having a first state in which said protection circuit providesan impedance greater than an operating impedance between said conductorand said substrate and a second state in which said protection circuitprovides a shorting impedance between said conductor and said substrate,said protection circuit being in said first state if the potential onsaid conductor is in an operating range defined by a negative thresholdpotential and a positive threshold potential, and said protectioncircuit being in said second state if said potential on said conductoris outside said operating range; and connecting said gate electrodes tosaid protection circuit by a metal layer.
 9. The method of claim 8wherein said process comprises a PMOS process and wherein saidprotection circuit comprises an NPN bipolar transistor and a PNP bipolartransistor with its base shorted to ground.
 10. The method of claim 8wherein said process comprises an NMOS process and wherein saidprotection circuit comprises a PNP bipolar transistor and an NPN bipolartransistor with its base shorted to ground.